Logic cloning based approximate signed multiplication circuits for FPGA

Kulkarni, A., Ouameur, M. A. et Massicotte, D. (2024). Logic cloning based approximate signed multiplication circuits for FPGA. Microelectronics Journal, 145 . p. 106135. ISSN 1879-2391 DOI 10.1016/j.mejo.2024.106135

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Résumé

As hardware circuits become larger and more intricate, there is a growing need for approximate circuit techniques. These approaches offer a trade-off, sacrificing some system accuracy in exchange for greater hardware resource efficiency and energy conservation. In the context of FPGA-based computation-intensive arithmetic multiplication, Logic Cloning (LC) is introduced to systematically induce controlled approximation. LC-Baugh Wooley (BW) circuits deliver exceptional error performance with precise approximation, while LC-Booth circuits are characterized by reduced Look-Up Table (LUT) resource consumption. In the case of 16-bit operands, LC methods effectively reduce LUT resource consumption by 31.05% for Booth and 36.85% for BW. Additionally, compared to their accurate counterparts, they lower the Power Delay Product (PDP) by 34% for Booth and 35% for BW. When it comes to symbol error-rate performance for Zero Forcing (ZF) Multiple Input Multiple Output (MIMO) uplink detection, these LC approximate multiplication circuits exhibit robust performance, particularly LC-BW circuits, which closely match the accuracy of ZF detection, followed by LC-Booth circuits.

Type de document:	Article
Mots-clés libres:	Approximate computing Reconfigurable computing Logic cloning Arithmetic multiplication Massive MIMO
Date de dépôt:	20 août 2025 18:10
Dernière modification:	20 août 2025 18:10
URI:	https://depot-e.uqtr.ca/id/eprint/12218

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